The present disclosure relates to symmetric multiprocessing systems (SMPs), and more specifically, to hot cache line arbitration within a processor cluster of multiple chip multiprocessors in a highly distributed SMP system.
In a highly distributed large symmetric multiprocessing (SMP) systems with decentralized cache line access arbitration, the amount of system time spent on cache to cache intervention for a common semaphore/lock address can be significantly higher than the lock time per processor, which may cause system responsiveness issues. As the SMP size continues to grow, this responsiveness issue will also grow.
It may be advantageous to ensure locking fairness across multiple processors and to improve locked time efficiency by minimizing the time an available semaphore/lock address is in transit between processors.